1. Technical Field
The present invention relates to a method for manufacturing the semiconductor device and a semiconductor device manufactured by such process.
2. Related Art
In recent years, high-density installation in a semiconductor device requires an increased number of lands disposed in one chip. In particular, configurations of flip-chip devices are advantageous for achieving an arrangement of larger number of lands, since such configurations allow installing lands in array-like patterns in both the periphery of the semiconductor device and additionally the entire surface of the semiconductor device.
In such flip-chip devices, bumps are formed by printing, vapor deposition, plating processes or the like on the lands, which is formed on the semiconductor element via a semiconductor process. A dicing process is conducted for the obtained product, and then the diced products are installed on the package substrate via a reflow soldering process to complete the production of the device.
An operability of a semiconductor device for a desired operation is required to be checked in a wafer-condition.
A large scale integration (LSI) tester is a device for applying electrical signal to a semiconductor element in a wafer-condition and determining whether the signal from the semiconductor element is a desired signal or not. A probe card is a tool utilized between a LSI tester and a semiconductor element and serves as transferring electrical signal. A probe card typically includes a probe card board for providing a coupling with a LSI tester and probes for providing contacts with lands on the semiconductor wafer.
In the case of the flip-chip device, the probes are required to be arranged in a probe card board in an array-like pattern with the same spacing as the spacing for the lands in the semiconductor wafer. In addition, larger number of lands causes narrower inter-pad distance. When a testing of a semiconductor wafer for such flip-chip device is conducted, electric contacts are assured by pushing the probes over bumps formed in the lands in the semiconductor wafer.
The coupling terminals that provide coupling to the LSI tester are required to be arranged around the circumference of the surface of the probe card board at predetermined spacing. In addition, the coupling terminals that provide coupling to the probes are required to be arranged around the center of the back surface of the probe card board in the same arrangement as employed for the lands on the semiconductor wafer. Therefore, it is concluded that, when the inter-probe distance or probe spacing is different from the inter-terminal distance or terminal spacing for the coupling terminals in the LSI tester, it is necessary to provide a matching of the spacing in the probe card board.
To solve the problem, either a wiring-system or an adapter board-system is employed for converting the spacing.
In the wiring-system, wires are laced through the board, which includes through holes corresponding to the spacing of the land pads in the semiconductor element, and the wires are cut and polished in the back surface of the board, and the cut surfaces of the wires are employed as the land pads in the side of the probes. The other ends of the wires are connected to the probe card board to obtain the coupling between the LSI tester and the probe.
In the case of employing the wiring system, all the procedures for electric wirings are made by manual works of workers. Limited number of electric wirings is available in the wiring system by such reasons, and more specifically the upper limit would be about 2,000 pins.
Therefore, when more pads are required, the use of the adapter board system is required. In order to manufacture land pads that accommodate narrower inter-pad distance of several hundred micrometers, ceramic boards or built-up boards are generally employed for the base material in the adapter board system. The set of the land pads are formed in the side of the back surface of the adapter board at the same inter-pad distance as employed in the semiconductor element, and the other set of the land pads are formed in the side of the front surface thereof at the inter-pad distance of about 1 mm, and wiring couplings are made between the set of land pads in the side of the back surface and the set of the land pads in the side of the front surface in the inside of the adapter board.
However, according to the adapter board system, new adapter board dedicated for the product must be designed in accordance with the arrangement of the pads specified for the product. Ceramics boards and the built-up boards, which are the materials for the base material in the adapter board system, are expensive, and therefore the adapter board system is not advantageous in terms of the cost.
To solve the problem, a technology employing the package substrate of the device as the adapter board has been developed, as described in Japanese Patent Laid-Open No. H07-301642 (1995). This allows reducing the cost for every device. FIG. 8 is a diagram, illustrating an exemplary implementation that employs a package substrate for an adapter board.
However, even if the configuration for utilizing the product package substrate of the object device is adopted as an adapter board as typically described in Japanese Patent Laid-Open No. H07-301642 (1995), the configuration further needs to be improved.
The adapter board is required to have a testing-dedicated terminal (testing-dedicated pads). The testing-dedicated pad is a dedicated terminal, which is essential for applying specified electrical signal from a LSI tester, when an LSI testing is conducted for an LSI formed in the semiconductor wafer. On the other hand, no terminals dedicated for the testing is required in the package substrate having a semiconductor device installed therein. Therefore, a direct utilization of the package substrate for the adapter board cannot achieve the LSI testing.
To solve the problem, wiring of the testing-dedicated pad on the package substrate is considered. Typical semiconductor packages having testing-dedicated pads are described in Japanese Patent Laid-Open No. 2003-347,482 and Japanese Patent Laid-Open No. 2004-022,664.
However, Japanese Patent Laid-Open No. 2003-347,482 merely discloses a configuration having a testing-dedicated pad provided only in the upper surface of the semiconductor package, and coupled to the semiconductor chip, and no package substrate testing-dedicated pad is provided in the configuration disclosed in Japanese Patent Laid-Open No. 2003-347,482. Further, no inter-pad distance conversion for the land pads is considered in the disclosure of Japanese Patent Laid-Open No. 2004-022,664. Therefore, the package substrate cannot be utilized for the adapter board for inspection that is employed for the conversion of the inter-pad distances in the above-described technologies disclosed in Japanese Patent Laid-Open No. 2003-347,482 and Japanese Patent Laid-Open No. 2004-022,664.
Further, if the semiconductor package is to be installed on a mother board, it is necessary to provide an external coupling terminal such as a solder bump and the like in a surface of opposite to the surface for installing the semiconductor element of the package substrate. However, when the terminals dedicated for the testing is wired on the package substrate, the presence of the solder bumps coupled on the testing-dedicated pad for the external coupling terminal may possibly limit flexibility for designing the mother board in the product having the package substrate installed therein.